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CY7C1300A
128K X 36 Dual I/O Dual Address Synchronous SRAM
Features
* * * * * * * * * * * * * * * * Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V -5% and +5% power supply VCC Separate VCCQ for output buffer Two chip enables for simple depth expansion Address, data input, CE1X, CE2X, CE1Y, CE2Y, PTX, PTY, WEX, WEY, and data output registers on-chip Concurrent Reads and Writes Two bidirectional data buses Can be configured as separate I/O Pass-through feature Asynchronous output enables (OEX, OEY) LVTTL-compatible I/O Self-timed Write Automatic power-down 176-pin TQFP package The CY7C1300A allows the user to concurrently perform Reads, Writes, or pass-through cycles in combination on the two data ports. The two address ports (AX, AY) determine the Read or Write locations for their respective data ports (DQX, DQY). All input pins except output enable pins (OEX, OEY) are gated by registers controlled by a positive-edge-triggered clock (CLK) input. The synchronous inputs include all addresses, data inputs, depth-expansion chip enables (CE1X, CE2X, CE1Y and CE2Y), pass-through controls (PTX and PTY), and Read-Write control (WEX and WEY). The pass-through feature allows data to be passed from one port to another, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass-through operation takes precedence over a Read operation. When AX and AY are the same, certain protocols are followed. If both ports are Read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array. The CY7C1300A operates from a +3.3V power supply. All inputs and outputs are LVTTL-compatible. These dual I/O, dual address synchronous SRAMs are well suited for ATM, Ethernet switches, routers, cell/frame buffers, SNA switches, and shared memory applications. The CY7C1300A needs one extra cycle after power for proper power-on reset. The extra cycle is needed after VCC is stable on the device. This device is available in a 176-pin TQFP package. Logic Block Diagram[1]
Functional Description
The CY7C1300A SRAM integrates 131,072 x 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.
Y
Note: 1. For 128K x 36 devices, AX and AY are 17-bit-wide buses.
Cypress Semiconductor Corporation Document #: 38-05075 Rev. *C
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised January 19, 2003
CY7C1300A
Selection Guide
-100 Maximum access time Maximum operating current Maximum CMOS standby current
Shaded areas contain advance information.
-83 6.0 430 100
Unit ns mA mA
5.0 500 100
Pin Configuration
176-pin TQFP
VSS DQY19 DQX19 VSS VCCQ DQY18 DQX18 AX6 AY6 AX7 AY7 VSS NC NC NC VSS NC NC CE2Y CE1Y# CLK VCC VSS OEY# OEX# CE2X CE1X# WEY# WEX# PTY# PTX# AX8 AY8 AX9 AY9 AX17* AY17* DQX17 DQY17 VCC VSS DQX16 DQY16 VSS VSS DQX20 DQY20 VCCQ VSS DQX21 DQY21 DQX22 DQY22 VCCQ VSS DQX23 DQY23 DQX24 DQY24 VCCQ VSS DQX25 DQY25 DQX26 DQY26 VCC VSS DQY27 DQX27 DQY28 DQX28 VCCQ VSS DQY29 DQX29 DQY30 DQX30 VCCQ VSS DQY31 DQX31 DQY32 DQX32 VCCQ VSS DQY33 DQX33 VSS
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
VSS DQX15 DQY15 VSS VCCQ DQX14 DQY14 DQX13 DQY13 VSS VCCQ DQX12 DQY12 DQX11 DQY11 VSS VCCQ DQX10 DQY10 DQX9 DQY9 VSS VCC DQY8 DQX8 DQY7 DQX7 VSS VCCQ DQY6 DQX6 DQY5 DQX5 VSS VCCQ DQY4 DQX4 DQY3 DQX3 VSS VCCQ DQY2 DQX2 VSS
Document #: 38-05075 Rev. *C
VSS DQY34 DQX34 VSS VCCQ DQY35 DQX35 VSS VSS AY5 AX5 AY4 AX4 AY3 AX3 AY2 AX2 AY1 AX1 AY0 AX0 VSS VCC AX10 AY10 AX11 AY11 AX12 AY12 AX13 AY13 AX14 AY14 AX15 AY15 AX16 AY16 DQX0 DQY0 VCCQ VSS DQX1 DQY1 VSS
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CY7C1300A
Pin Definitions
Name AX0- AX16 AY0- AY16 WEX WEY PTX PTY OEX OEY DQX0- DQX35 DQY0- DQY35 CLK CE1X CE2X CE1Y CE2Y VCC VSS VSS VCCQ NC I/O Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous Input Input Input/ Output Input/ Output Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous Supply Ground Ground I/O Supply - Description Synchronous Address Inputs of Port X: Do not allow address pins to float. Synchronous Address Inputs of Port Y: Do not allow address pins to float. Read Write of Port X: WEX signal is a synchronous input that identifies whether the current loaded cycle is a Read or Write operation. Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current loaded cycle is a Read or Write operation. Pass-Through of Port X: PTX signal is a synchronous input that enables passing Port X input to Port Y output. Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input to Port X output. Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH, the DQXx pins are in high-impedance state. Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH, the DQYx pins are in high-impedance state. Data Inputs/Outputs of Port X: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Clock: This is the clock input to this device. Except for OEX and OEY, all timing references of the address, data in, and all control signals for the device are made with respect to the rising edge of CLK. Synchronous Active LOW Chip Enable Port X: CE1X is used with CE2X to enable Port X of this device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for Port X. Synchronous Active HIGH Chip Enable Port X: CE2X is used with CE1X to enable Port X of this device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for Port X. Synchronous Active LOW Chip Enable Port Y: CE1Y is used with CE2Y to enable Port Y of this device. CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for Port Y. Synchronous Active HIGH Chip Enable Port Y: CE2Y is used with CE1Y to enable Port Y of this device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for Port Y. Power Supply: +3.3V -5% and +5%. Ground: GND. Ground: GND. No chip current flows through these pins. However, the user needs to connect GND to these pins. Output Buffer Supply: +3.3V -5% and +5%. No Connect: These signals are not internally connected. The user can connect them to VCC, VSS, or any signal lines, or simply leave them floating.
[2, 3, 4, 5, 6, 7, 8, 9]
Cycle Description Truth Table
Operation Deselect Cycle Deselect Cycle Write Port X CE1X H X L
CE2X X L H
CE1Y H X X
CE2Y X L X
WEX X X 0
WEY X X X
PTX X X X
PTY X X X
Notes: 2. X means "Don't Care." H means logic HIGH. L means logic LOW. 3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For Write and Pass-through operations following a Read operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data hold time. 5. Operation numbers 3-6 can be used in any combination. 6. Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined. 7. Operation numbers 5 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation. 8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation. 9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up
Document #: 38-05075 Rev. *C
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CY7C1300A
Cycle Description Truth Table (continued)[2, 3, 4, 5, 6, 7, 8, 9]
Operation Write Port Y Pass-through from X to Y Pass-through from Y to X Read Port X Read Port Y CE1X X L L L X CE2X X H H H X CE1Y L L L X L CE2Y H H H X H WEX X X X 1 X WEY 0 X X X 1 PTX X 0 X 1 1 PTY X X 0 1 1
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -55C to +125C Ambient Temperature with Power Applied.................................................... -10C to +85C Supply Voltage on VDD Relative to GND.........-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[10] ...................................-0.5V to VCCQ + 0.5V DC Input Voltage[10] ................................-0.5V to VCCQ + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ......................................... > 1601V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature[11] 0C to +70C VDD/VDDQ(12) 3.3V 5%
Electrical Characteristics Over the Operating Range
Paramete r VDD VDDQ VOH VOL VIH VIL IX IOZ ICC ISB Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[13] Input LOW Voltage[14] Input Load Current Output Leakage Current VDD Operating Supply Automatic CE Power-down Current--CMOS Inputs GND VIN VDDQ GND VIN VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected , VIN 0.3V or VIN > VDDQ - 0.3V, f=0
[15]
Test Conditions
Min. 3.135 3.135
Max. 3.465 3.465 0.4
Unit V V V V V V A A mA mA mA mA
VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA
2.4 2.0 -0.5 -5 -5 VCC + 0.5V 0.8 5 5 500 430 140 120
10.0 ns cycle, MHz 12.0 ns cycle, 83 MHz 10.0 ns cycle, 100 MHz 12.0 ns cycle, 83 MHz
Capacitance[16]
Parameter CIN CCLK Description Input capacitance Clock input capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V, VCCQ = 3.3V Max. 8 9 Unit pF pF
Notes: 10. Minimum voltage equals -2.0V for pulse duration less than 20 ns. 11. TA is the case temperature. 12. Power supply ramp up should be monotonic. 13. Overshoot: VIH +6.0V for t tKC /2. 14. Undershoot: VIL -2.0V for t tKC /2. 15. "Device Deselected" means the device is in power-down mode as defined in the truth table. 16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05075 Rev. *C
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CY7C1300A
AC Test Loads and Waveforms[17, 18]
OUTPUT Z0 = 50 RL = 50 VL = 1.5V 3.3V OUTPUT 3.0V 5 pF R = 351 GND INCLUDING JIG AND SCOPE
1V/ns 1V/ns
R = 317 ALL INPUT PULSES
[17]
(a)
(b)
(c)
Thermal Resistance
Parameter JA JC JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Board) Thermal Resistance (Junction to Case) Test Conditions (@200lfm) Single-layer printed circuit board (@200lfm) Four-layer printed circuit board Bottom Top TQFP Typ. 40 35 23 9 Units C/W C/W C/W C/W Notes 15 15 15 15
Notes: 17. AC test conditions assume a signal transition time of 1 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in part (a) of AC Test Loads. 18. Overshoot: VIH(AC) Document #: 38-05075 Rev. *C
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CY7C1300A
Switching Characteristics Over the Operating Range[17, 19, 20]
-100 Parameter Clock tKC tKH tKL Output times tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Set-up times tS Hold times tH Clock cycle time Clock HIGH time Clock LOW time Clock to output valid Clock to output invalid Clock to output in Low-Z
[21] [21]
-83 Max. Min. 12 4.0 4.0 5.0 6.0 1.5 0 3.0 5.0 3.0 6.0 0 3.0 3.0 2.0 0.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Description
Min. 10 3.5 3.5
1.5 0
Clock to output in High-Z
OEX/OEY to output valid OEX/OEY to output in Low-Z
[21] [21]
0
OEX/OEY to output in High-Z
Addresses, controls, and data In Addresses, controls, and data In
1.8 0.5
Notes: 19. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions, as shown in part (a) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but rather reflect parameters guaranteed over worst-case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested.
Document #: 38-05075 Rev. *C
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CY7C1300A
Switching Waveforms [22]
Read Cycle Timing from Both Ports (WEX, WEY, PTX, PTY HIGH)[22]
t
KC
tKL
CLK
tS tKH
AX
1
2
tH
3
4
5
6
7
8
t
9
OEQ
PORT X
OEX#
tKQ tOEHZ
DQX CE# (See Note) AY 12 13
Q(1)
Q(2)
Q(3)
Q(5)
t
Q(6)
Q(7)
t
OELZ
S
tH
14
15
16
6
7
19
20
PORT Y
OEY#
tKQHZ
tKQLZ
DQY
Q(12)
Q(13)
Q(14)
t
Q(16)
KQ
Q(6)
Q(7)
22. CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH means (CE1X and CE1Y) equals HIGH or (CE2X and CE2Y) equals LOW.
Document #: 38-05075 Rev. *C
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CY7C1300A
Switching Waveforms (continued)[22]
Write Cycle Timing to Both Ports (PTX, PTY HIGH)[21]
tKC tKL
CLK
tKH
AX
1
2
t
3
H
4
5
6
7
8
9
WEX# PORT X OEX#
tS tS tH
DQX CE# (See Note) AY 12
D(2)
D(3)
D(4)
t
D(8)
S
D(9)
tH
13
14
15
5
6
18
19
20
WEY# PORT Y OEY#
DQY
D(14)
D(15)
D(5)
D(6)
D(18)
D(19)
PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH
Document #: 38-05075 Rev. *C
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CY7C1300A
Switching Waveforms (continued)[22]
Write to Port X and Pass-through to Port Y[21]
tKC tKL
CLK
tKH
AX
1
2
3
4
5
6
7
8
9
WEX#
PORT X
OEX#
tH
PTX# PTY#
tS tH tS
DQX CE# (See Note) AY 12
D(2)
D(3)
D(X)
D(Y)
D(6)
13
14
15
16
17
18
19
20
WEY#
PORT Y
OEY#
PTY#
tKQ tKQHZ
DQY
Q(3)
t
D(X)
KQX
D(Y)
Q(17)
Document #: 38-05075 Rev. *C
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CY7C1300A
Switching Waveforms (continued)[22]
Combination Read/Write with Same Address on Each Port
tKC tKL t
KH
CLK
TRY TO WRITE TRY TO WRITE READ READ READ READ READ READ
AX
1
2
t
1
H
2
3
WEX# PORT X OEX#
tS
DQX
D(ABC)
D(DEF)
Q(PQR)
Q(XYZ)
Q(JKL)
WRITE
WRITE
READ
READ
READ
READ
READ
READ
AY
1
2
1
2
3
WEY# PORT Y OEY#
DQY
D(PQR)
D(XYZ)
Q(PQR)
D(JKL)
Q(JKL)
PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH PORTS.
PTX# = PTY# = HIGH D(Value) = Value is the input of the data port. Q(Value) = Value is the output of the data port.
Document #: 38-05075 Rev. *C
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CY7C1300A
Ordering Information
Speed (MHz) 100 83 Ordering Code CY7C1300A-100AC CY7C1300A-83AC Package Name AC Package Type 176-lead TQFP Operating Range Commercial
Package Diagram
176-lead Thin Quad Flat Pack (24 x 24 x 1.4 mm) A176
51-85132
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05075 Rev. *C
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1300A
Document Title: CY7C1300A 128K x 36 Dual I/O Dual Address Synchronous SRAM Document Number: 38-05075 REV. ** *A ECN NO. 107304 109296 Issue Date 06/08/01 10/31/01 Orig. of Change NSL CJM Description of Change New Data Sheet 1. Removed 133 MHz speed bin 2. Changed ESD voltage from >2001V to >1601V 3. Changed tS from 1.5 ns to 1.8 ns (only 100 MHz) 4. Changed ISB from 100 mA to 120 mA (All speeds) 5. Changed CIN from 6 pF to 8 pF (All speeds) 6. Changed CCLK from 6 pF to 9 pF (All speeds) 7. Changed ICC to reflect char data (All speeds) 8. Changed ordering code from CY7C1301A to CY7C1300A (All speeds) 9. Removed Preliminary Changed ICC values on first page to correct value (500 and 430). Also updated Logic Block Diagram. Updated power-up requirements in Operating Range and in AC Test Loads and Waveforms.
*B *C
113017 123844
04/09/02 01/19/03
KOM AJH
Document #: 38-05075 Rev. *C
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